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# GATE Electronics & Communication Vol-6- Digital Electronics

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PUBLISHED FOR GATE 2018

 Edition 8th Authors R K Kanodia & Ashish Murolia Publisher NODIA Pages 626 Binding Paper Back Language English

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SALIENT FEATURES

• Brief Theory

• Problem Solving Methodology

• Fundamental Concepts & Formulae Review

• Vast Question book with Full Solutions

• Multiple Choice Questions, Memory Based Questions and Numerical Types Questions

• Full width coverage of GATE Syllabus

• Well explained and error free solutions

CHAP 1 NUMBER SYSTEM AND CODES

1.1 INTRODUCTION

1.2 ANALOG AND DIGITAL SYSTEMS

1.2.2 Limitations of Digital System

1.3 NUMBER SYSTEMS

1.3.1 Decimal Number System

1.3.2 Binary Number System

1.3.3 Octal Number System

1.4 NUMBER SYSTEM CONVERSION

1.4.1 Decimal-to-Binary Conversion

1.4.2 Decimal-to-Octal Conversion

1.4.4 Octal-to-Binary conversion

1.4.5 Binary-to-Octal Conversion

1.5 BASIC BINARY ARITHMETIC

1.5.2 Binary Subtraction

1.5.3 Binary Multiplication

1.5.4 Binary Division

1.6 COMPLEMENTS OF NUMBERS

1.7 NUMBER REPRESENTATION IN BINARY

1.7.1 Sign-Magnitude Representation

1.7.2 1's Complement Representation

1.7.3 2's Complement Representation

1.8 COMPLEMENT BINARY ARITHMETIC

1.8.2 Subtraction Using 1â€™s Complement

1.8.4 Subtraction using 2â€™s Complement

1.9.1 Hexadecimal Arithmetic Using 1â€™s or 2â€™s Complements

1.9.2 Hexadecimal Subtraction Using 15â€™s or 16â€™s Complement

1.10 OCTAL ARITHMETIC

1.10.1 Octal Arithmetic using 1â€™s or 2â€™s Complements

1.10.2 Octal Subtraction using 7â€™s or 8â€™s complement

1.11 DECIMAL ARITHMETIC

1.11.1 Decimal Arithmetic Using 1â€™s or 2â€™s Complements

1.11.2 Decimal Subtraction Using 9â€™s and 10â€™s Complement

1.12 BINARY CODES

1.13 BINARY CODED DECIMAL (BCD) CODE OR 8421 CODE

1.13.1 BCD-to-Binary Conversion

1.13.2 Binary-to-BCD Conversion

1.14 BCD ARITHMETIC

1.14.2 BCD Subtraction

1.15 THE EXCESS-3 CODE

1.16 GRAY CODE

1.16.1 Binary-to-Gray Code Conversion

1.16.2 Gray-to-Binary Code Conversion

1.16.3 Applications of Gray Code

EXERCISE 1.1

EXERCISE 1.2

EXERCISE 1.3

SOLUTIONS 1.1

SOLUTIONS 1.2

SOLUTIONS 1.3

CHAPTER 2 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

2.1 INTRODUCTION

2.2 BOOLEAN ALGEBRA

2.2.1 Logic Levels

2.2.2 Truth Table

2.3 BASIC BOOLEAN OPERATIONS

2.3.2 Boolean Multiplication (Logical AND)

2.3.3 Logical NOT

2.4 THEOREMS OF BOOLEAN ALGEBRA

2.4.1 Complementation Laws

2.4.2 AND Laws

2.4.3 OR Laws

2.4.4 Commutative Laws

2.4.5 Associative Laws

2.4.6 Distributive Law

2.4.7 Redundant Literal Rule

2.4.8 Idempotent Law

2.4.9 Absorption Law

2.4.10 Consensus Theorem

2.4.11 Transposition Theorem

2.4.12 De Morganâ€™s Theorem

2.4.13 Shannonâ€™s Expansion Theorem

2.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA

2.5.1 Complement of Boolean Function

2.5.2 Principal of Duality

2.5.3 Relation Between Complement and Dual

2.6 LOGIC GATES

2.6.1 Logic Levels

2.6.2 Types of Logic Gates

2.7 UNIVERSAL GATE

2.7.1 NAND Gate as a Universal Gate

2.7.2 NOR Gate as a Universal Gate

2.8 ALTERNATE LOGIC-GATE REPRESENTATIONS

2.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS

2.9.1 Converting Boolean Expressions to Logic Diagram

2.9.2 Converting Logic to Boolean Expressions

2.10 CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC

2.10.1 NAND-NAND Logic

2.10.2 NOR-NOR Logic

EXERCISE 2.1

EXERCISE 2.2

EXERCISE 2.3

SOLUTIONS 2.1

SOLUTIONS 2.2

SOLUTIONS 2.3

CHAPTER 3 THE K-MAP

3.1 INTRODUCTION

3.2 REPRESENTATION FOR BOOLEAN FUNCTIONS

3.2.1 Sum-of-Products (SOP)

3.2.2 Product-of-Sum (POS)

3.3 STANDARD OR CANONICAL SUM-OF-PRODUCTS (SOP) FORM

3.3.1 Minterm

3.3.2 Î£ Notation

3.3.3 Converting SOP Form to Standard SOP Form

3.4 STANDARD OR CANONICAL PRODUCT-OF-SUMS (POS) FORM

3.4.1 Maxterm

3.4.2 Î Notation

3.4.3 Converting POS Form to standard POS Form

3.5 CONVERTING STANDARD SOP FORM TO STANDARD POS FORM

3.6 BOOLEAN EXPRESSIONS AND TRUTH TABLES

3.7 CALCULATION OF TOTAL GATE INPUTS USING SOP AND POS

3.8 KARNAUGH MAP (K-MAP)

3.8.1 Structure of K-map

3.8.2 Another Structure of K-map

3.9 PLOTTING A K-MAP

3.9.1 Plotting Standard SOP on K-map

3.9.2 Plotting Standard POS on K-map

3.9.3 Plotting a Truth Table on K-map

3.10 GROUPING OF CELLS FOR SIMPLIFICATION

3.10.1 Grouping of Two adjacent Cells (Pair)

3.10.3 Grouping of Eight Adjacent Cells (Octet)

3.10.4 Redundant Group

3.11 MINIMIZATION OF SOP EXPRESSIONS

3.12 MINIMIZATION OF POS EXPRESSIONS

3.13 CONVERTING SOP TO POS AND VICE-VERSA

3.14 DONâ€™T CARE CONDITIONS

3.14.1 K-map Simplification With Donâ€™t Care Conditions

3.14.2 Conversion of Standard SOP to Standard POS with Donâ€™t Care Conditions

3.15 K-MAPS FOR MULTI-OUTPUT FUNCTIONS

3.16 LIMITATIONS OF K-MAP

EXERCISE 3.1

EXERCISE 3.2

EXERCISE 3.3

SOLUTIONS 3.1

SOLUTIONS 3.2

SOLUTIONS 3.3

CHAPTER 4 COMBINATIONAL CIRCUITS

4.1 INTRODUCTION

4.2 DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS

4.4 SUBTRACTORS

4.4.1 Half-Subtractor

4.4.2 Full-Subtractor

4.6.1 Carry Generation

4.6.2 Carry Propagation

4.8 COMPARATOR

4.8.1 1-bit Magnitude Comparator

4.8.2 2-bit Magnitude Comparator

4.9 MULTIPLEXER

4.9.1 2-to-1 Multiplexer

4.9.2 4-to-1 Multiplexer

4.9.3 Implementation of Higher Order Multiplexers using Lower Order Multiplexers

4.9.4 Applications of Multiplexers

4.10 DEMULTIPLEXER

4.10.1 1-to-2 Demultiplexer

4.10.2 1-to-8 Demultiplexer

4.10.3 Applications of Demultiplexers

4.10.4 Comparison between Multiplexer and Demultiplexer

4.11 DECODER

4.11.1 2-to-4 Line Decoder

4.11.2 Applications of Decoder

4.12 ENCODERS

4.12.1 Octal-to-Binary Encoder

4.12.2 Decimal-to-BCD Encoder

4.13 PRIORITY ENCODERS

4.14 CODE CONVERTERS

4.15 PARITY GENERATOR

4.15.1 Even Parity Generator

4.15.2 Odd Parity Generator

EXERCISE 4.1

EXERCISE 4.2

EXERCISE 4.3

SOLUTIONS 4.1

SOLUTIONS 4.2

SOLUTIONS 4.3

CHAPTER 5 SEQUENTIAL CIRCUITS

5.1 INTRODUCTION

5.2 SEQUENTIAL LOGIC CIRCUITS

5.3 LATCHES AND FLIP-FLOPS

5.3.1 General Block Diagram of a Latch or Flip-flop

5.3.2 Difference between Latches and Flip-flops

5.4 S-R LATCH

5.4.1 S -R Latch using NOR Gates

5.4.2 S -R Latch using NAND Gates

5.5 FLIP-FLOPS

5.5.1 S-R Flip-Flop

5.5.2 D-Flip Flop

5.5.3 J-K Flip-Flop

5.5.4 T Flip-Flop

5.6 TRIGGERING OF FLIP-FLOPS

5.6.1 Level Triggering

5.6.2 Edge Triggering

5.6.3 Edge Triggered S -R Flip Flop

5.6.4 Edge Triggered D Flip-Flop

5.6.5 Edge Triggered J -K Flip-Flop

5.6.6 Edge Triggered T -Flip-Flop

5.7 OPERATING CHARACTERISTIC OF FLIP-FLOPS

5.8 APPLICATION OF FLIP-FLOPS

5.9 REGISTER

5.9.1 Buffer Register

5.9.2 Shift Register

5.9.3 Applications of Shift Registers

5.10 COUNTER

5.10.1 Asynchronous and Synchronous Counter

5.10.2 Up-Counter and Down-Counter

5.10.3 MOD Number or Modulus of a Counter

5.11 SHIFT REGISTER COUNTERS

5.11.1 Ring Counter

5.11.2 Johnson Counter

EXERCISE 5.1

EXERCISE 5.2

EXERCISE 5.3

SOLUTIONS 5.1

SOLUTIONS 5.2

SOLUTIONS 5.3

CHAPTER 6 LOGIC FAMILIES

6.1 INTRODUCTION

6.2 CLASSIFICATION OF DIGITAL LOGIC FAMILY

6.3 CHARACTERISTIC PARAMETERS OF DIGITAL LOGIC FAMILY

6.3.1 Speed of Operation

6.3.2 Power Dissipation

6.3.3 Voltage Parameters

6.3.4 Current Parameters

6.3.5 Noise Immunity or Noise Margin

6.3.6 Fan-In

6.3.7 Fan-out

6.3.8 Operating Temperature

6.3.9 Speed Power Product

6.4 RESISTOR-TRANSISTOR LOGIC (RTL)

6.4.1 Circuit Operation

6.4.2 Drawbacks of RTL Family

6.5 DIRECT COUPLED TRANSISTOR LOGIC (DCTL)

6.5.1 Circuit Operation

6.6 DIODE TRANSISTOR LOGIC (DTL)

6.7 TRANSISTOR-TRANSISTOR LOGIC (TTL)

6.8 TTL CIRCUIT OUTPUT CONNECTION

6.8.1 Totem-pole Output

6.8.2 Open-collector Output

6.8.3 Tri-state Output

6.9 TTL SUBFAMILIES

6.10 EMITTER COUPLED LOGIC (ECL)

6.10.1 ECL OR/NOR Gate

6.10.2 ECL Characteristics

6.11 INTEGRATED INJECTION LOGIC (I2L)

6.11.1 Characteristic of I2L

6.11.2 I2L Inverter

6.11.3 I2L NAND Gate

6.11.4 I2L NOR Gate

6.12 METAL OXIDE SEMICONDUCTOR (MOS) LOGIC

6.12.1 NMOS Inverter

6.12.2 NMOS NAND Gate

6.12.3 NMOS NOR Gate

6.12.4 Characteristics of MOS Logic

6.13 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) LOGIC

6.13.1 CMOS Inverter

6.13.2 CMOS NAND Gate

6.13.3 CMOS NOR Gate

6.13.4 Characteristics of CMOS Logic

6.14 COMPARISON OF VARIOUS LOGIC FAMILIES

EXERCISE 6.1

EXERCISE 6.2

EXERCISE 6.3

SOLUTIONS 6.1

SOLUTIONS 6.2

SOLUTIONS 6.3

CHAPTER 7 INTERFACING TO ANALOG

7.1 INTRODUCTION

7.2 DIGITAL TO ANALOG CONVERTER

7.2.1 Parameters of DAC

7.3 DAC CIRCUITS

7.3.2 Weighted Resistor Type DAC

7.4 ANALOG-TO-DIGITAL CONVERTER

7.4.1 Sample-and-hold circuit

7.4.2 Quantization and Encoding

7.5.1 Flash Type A/D Converter

7.5.2 Counting A/D Converter

7.5.3 Dual Slope Type A/D Converter

7.6 ASTABLE MULTIVIBRATOR

7.6.1 Astable Multivibrator Using BJT

7.6.2 Astable Multivibrator Using 555 Timer

7.6.3 Astable Multivibrator Using Op-amps

7.7 MONOSTABLE MULTIVIBRATOR

7.7.1 Monostable Multivibrator Using BJT

7.7.2 Monostable Multivibrator Using 555 Timer

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