-16%

# GATE Digital Logic

Product Code: CS-3
Availability: Out Of Stock

Special price:Rs 410.00
Old price:Rs 490.00
You save:Rs 80.00

PUBLISHED FOR GATE 2016

 Edition 1st Publisher NODIA Pages 632 Binding Paper Back Language English

## Write a review

Note: HTML is not translated!

SALIENT FEATURES

• Brief Theory

• Problem Solving Methodology

• Fundamental Concepts & Formulae Review

• Vast Question book with Full Solutions

• Multiple Choice Questions, Memory Based Questions and Numerical Types Questions

• Full width coverage of GATE Syllabus

• Well explained and error free solutions

CHAPTER 1 NUMBER REPRESENTATION

1.1 INTRODUCTION

1.2 ANALOG AND DIGITAL SYSTEMS

1.2.2 Limitations of Digital System

1.3 NUMBER SYSTEMS

1.3.1 Decimal Number System

1.3.2 Binary Number System

1.3.3 Octal Number System

1.4 NUMBER SYSTEM CONVERSION

1.4.1 Decimal-to-Binary Conversion

1.4.2 Decimal-to-Octal Conversion

1.4.4 Octal-to-Binary conversion

1.4.5 Binary-to-Octal Conversion

1.5 COMPLEMENTS OF NUMBERS

1.6 NUMBER REPRESENTATION IN BINARY

1.6.1 Sign-Magnitude Representation

1.6.2 1â€™s Complement Representation

1.6.3 2â€™s Complement Representation

1.7 FLOATING POINT REPRESENTATION

1.7.1 A Simple Model

1.7.2 IEEE Standard For Binary Floating Point Representation

CHAPTER 2 COMPUTER ARITHMETIC

2.1 BASIC BINARY ARITHMETIC

2.1.2 Binary Subtraction

2.1.3 Binary Multiplication

2.1.4 Binary Division

2.2 COMPLEMENT BINARY ARITHMETIC

2.2.2 Subtraction Using 1â€™s Complement

2.2.4 Subtraction using 2â€™s Complement

2.3.1 Hexadecimal Arithmetic Using 1â€™s or 2â€™s Complements

2.3.2 Hexadecimal Subtraction Using 15â€™s or 16â€™s Complements

2.4 OCTAL ARITHMETIC

2.4.1 Octal Arithmetic using 1â€™s or 2â€™s Complements

2.4.2 Octal Subtraction using 7â€™s or 8â€™s Complements

2.5 DECIMAL ARITHMETIC

2.5.1 Decimal Arithmetic Using 1â€™s or 2â€™s Complements

2.5.2 Decimal Subtraction Using 9â€™s and 10â€™s Complement

2.6 BINARY ARITHMETIC

2.7 BINARY CODES

2.8 BINARY CODED DECIMAL (BCD) CODE OR 8421 CODE

2.8.1 BCD-to-Binary Conversion

2.8.2 Binary-to-BCD Conversion

2.9 BCD ARITHMETIC

2.9.2 BCD Subtraction

2.10 THE EXCESS-3 CODE

2.11 GRAY CODE

2.11.1 Binary-to-Gray Code Conversion

2.11.2 Gray-to-Binary Code Conversion

2.11.3 Applications of Gray Code

2.12 FLOATING POINT ARITHMETIC

2.12.2 Multiplication and Division

2.12.3 IEEE Standard For Binary Floating Arithmetic

CHAPTER 3 LOGIC FUNCTION

3.1 INTRODUCTION

3.2 BOOLEAN ALGEBRA

3.2.1 Logic Levels

3.2.2 Truth Table

3.3 BASIC BOOLEAN OPERATIONS

3.3.2 Boolean Multiplication (Logical AND)

3.3.3 Logical NOT

3.4 THEOREMS OF BOOLEAN ALGEBRA

3.4.1 Complementation Laws

3.4.2 AND Laws

3.4.3 OR Laws

3.4.4 Commutative Laws

3.4.5 Associative Laws

3.4.6 Distributive Law

3.4.7 Redundant Literal Rule

3.4.8 Idempotent Law

3.4.9 Absorption Law

3.4.10 Consensus Theorem

3.4.11 Transposition Theorem

3.4.12 De Morganâ€™s Theorem

3.4.13 Shannonâ€™s Expansion Theorem

3.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA

3.5.1 Complement of Boolean Function

3.5.2 Principal of Duality

3.5.3 Relation Between Complement and Dual

3.6 LOGIC GATES

3.6.1 Logic Levels

3.6.2 Types of Logic Gates

3.7 UNIVERSAL GATE

3.7.1 NAND Gate as a Universal Gate

3.7.2 NOR Gate as a Universal Gate

3.8 ALTERNATE LOGIC-GATE REPRESENTATIONS

3.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS

3.9.1 Converting Boolean Expressions to Logic Diagram

3.9.2 Converting Logic to Boolean Expressions

3.10 CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC

3.10.1 NAND-NAND Logic

3.10.2 NOR-NOR Logic

CHAPTER 4 MINIMIZATION OF LOGIC FUNCTION

4.1 INTRODUCTION

4.2 REPRESENTATION FOR BOOLEAN FUNCTIONS

4.2.1 Sum-of-Products (SOP)

4.2.2 Product-of-Sum (POS)

4.3 STANDARD OR CANONICAL SUM-OF-PRODUCTS (SOP) FORM

4.3.1 Minterm

4.3.2 Î£ Notation

4.3.3 Converting SOP Form to Standard SOP Form

4.4 STANDARD OR CANONICAL PRODUCT-OF-SUMS (POS) FORM

4.4.1 Maxterm

4.4.2 Î Notation

4.4.3 Converting POS Form to standard POS Form

4.5 CONVERTING STANDARD SOP FORM TO STANDARD POS FORM

4.6 BOOLEAN EXPRESSIONS AND TRUTH TABLES

4.7 CALCULATION OF TOTAL GATE INPUTS USING SOP AND POS

4.8 KARNAUGH MAP (K-MAP)

4.8.1 Structure of K-map

4.8.2 Another Structure of K-map

4.9 PLOTTING A K-MAP

4.9.1 Plotting Standard SOP on K-map

4.9.2 Plotting Standard POS on K-map

4.9.3 Plotting a Truth Table on K-map

4.10 GROUPING OF CELLS FOR SIMPLIFICATION

4.10.1 Grouping of Two adjacent Cells (Pair)

4.10.3 Grouping of Eight Adjacent Cells (Octet)

4.10.4 Redundant Group

4.11 MINIMIZATION OF SOP EXPRESSIONS

4.12 MINIMIZATION OF POS EXPRESSIONS

4.13 CONVERTING SOP TO POS AND VICE-VERSA

4.14 DONâ€™T CARE CONDITIONS

4.14.1 K-map Simplification With Donâ€™t Care Conditions

4.14.2 Conversion of Standard SOP to Standard POS with Donâ€™t Care Conditions

4.15 K-MAPS FOR MULTI-OUTPUT FUNCTIONS

4.16 LIMITATIONS OF K-MAP

CHAPTER 5 DESIGN AND SYNTHESIS OF COMBINATIONAL CIRCUIT

5.1 INTRODUCTION

5.2 DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS

5.4 SUBTRACTORS

5.4.1 Half-Subtractor

5.4.2 Full-Subtractor

5.6.1 Carry Generation

5.6.2 Carry Propagation

5.8 COMPARATOR

5.8.1 1-bit Magnitude Comparator

5.8.2 2-bit Magnitude Comparator

5.9 MULTIPLEXER

5.9.1 2-to-1 Multiplexer

5.9.2 4-to-1 Multiplexer

5.9.3 Implementation of Higher Order Multiplexers using Lower Order Multiplexers

5.9.4 Applications of Multiplexers

5.10 DEMULTIPLEXER

5.10.1 1-to-2 Demultiplexer

5.10.2 1-to-8 Demultiplexer

5.10.3 Applications of Demultiplexers

5.10.4 Comparison between Multiplexer and Demultiplexer

5.11 DECODER

5.11.1 2-to-4 Line Decoder

5.11.2 Applications of Decoder

5.12 ENCODERS

5.12.1 Octal-to-Binary Encoder

5.12.2 Decimal-to-BCD Encoder

5.13 PRIORITY ENCODERS

5.14 CODE CONVERTERS

5.15 PARITY GENERATOR

5.15.1 Even Parity Generator

5.15.2 Odd Parity Generator

CHAPTER 6 DESIGN AND SYNTHESIS OF SEQUENTIAL CIRCUIT

6.1 INTRODUCTION

6.2 SEQUENTIAL LOGIC CIRCUITS

6.3 LATCHES AND FLIP-FLOPS

6.3.1 General Block Diagram of a Latch or Flip-flop

6.3.2 Difference between Latches and Flip-flops

6.4 S-R LATCH

6.4.1 S -R Latch using NOR Gates

6.4.2 S -R Latch using NAND Gates

6.5 FLIP-FLOPS

6.5.1 S-R Flip-Flop

6.5.2 D-Flip Flop

6.5.3 J-K Flip-Flop

6.5.4 T Flip-Flop

6.6 TRIGGERING OF FLIP-FLOPS

6.6.1 Level Triggering

6.6.2 Edge Triggering

6.6.3 Edge Triggered S-R Flip Flop

6.6.4 Edge Triggered D Flip-Flop

6.6.5 Edge Triggered J-K Flip-Flop

6.6.6 Edge Triggered T-Flip-Flop

6.7 OPERATING CHARACTERISTIC OF FLIP-FLOPS

6.8 APPLICATION OF FLIP-FLOPS

6.9 REGISTER

6.9.1 Buffer Register

6.9.2 Shift Register

6.9.3 Applications of Shift Registers

6.10 COUNTER

6.10.1 Asynchronous and Synchronous Counter

6.10.2 Up-Counter and Down-Counter

6.10.3 MOD Number or Modulus of a Counter

6.11 SHIFT REGISTER COUNTERS

6.11.1 Ring Counter

6.11.2 Johnson Counter

SALIENT FEATURES OF TEST SERIES

 10 Full Length Mock Tests 30 Subjectwise Tests 100 Topic Tests Descriptive Solution for Each Test Self Performance Analysis Compartive Analysis with Toppers View Demo  Click Here

*GATE Online Test Series is Free with the Purchase of this Book

Once, you place the order, we will forward your details to gatehelp team. In next 1-2 days you will get user id and password for logging in to gathelp.com and start your test.

Related Products
Designed By : xtensions
Copyright to : Nodia & Company All reversed