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GATE Electronics & Communication Vol-4- Electronics Devices

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PUBLISHED FOR GATE 2018

Edition 8th
Authors R K Kanodia & Ashish Murolia
Publisher NODIA
Pages 466
Binding Paper Back
Language English

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SALIENT FEATURES

  • Brief Theory

  • Problem Solving Methodology

  • Fundamental Concepts & Formulae Review

  • Vast Question book with Full Solutions

  • Multiple Choice Questions, Memory Based Questions and Numerical Types Questions

  • Full width coverage of GATE Syllabus

  • Well explained and error free solutions


TABLE OF CONTENTS

CHAPTER 1 SEMICONDUCTORS IN EQULIBRIUM

1.1 INTRODUCTION

1.2 SEMICONDUCTOR MODELS

1.2.1 Bonding Model

1.2.2 Energy Band Model

1.3 CARRIERS

1.3.1 Carrier Properties

1.4 INTRINSIC SEMICONDUCTOR

1.5 DOPING

1.5.1 n-type Semiconductor

1.5.2 p-type Semiconductor

1.6 COMPENSATED SEMICONDUCTOR

1.7 FERMI FUNCTION

1.7.1 Energy Dependence of Fermi Function

1.8 EQUILIBRIUM CARRIER CONCENTRATIONS

1.8.1 Intrinsic Carrier Concentration

1.8.2 Extrinsic Carrier Concentration

1.9 ENERGY BAND DIAGRAM FOR INSULATOR, SEMICONDUCTOR, AND METAL

1.9.1 Insulator

1.9.2 Semiconductor

1.9.3 Metal

1.10 POSITION OF FERMI ENERGY LEVEL

1.10.1 Fermi Energy Level for n-type Semiconductor

1.10.2 Fermi Energy Level for p-type Semiconductor

1.10.3 Variation of Fermi Level with Temperature

1.11 CHARGE NEUTRALITY

1.11.1 Determination of Thermal Equilibrium Electron Concentration as a Function of Impurity Doping Concentration

1.11.2 Determination of Thermal Equilibrium Hole Concentration as a Function of Impurity Doping Concentration

1.12 DEGENERATE AND NON DEGENERATE SEMICONDUCTORS

1.12.1 Non-degenerate Semiconductor

1.12.2 Degenerate Semiconductor

1.13 IMPORTANT PROPERTIES AND STANDARD CONSTANTS

EXERCISE 1.1

EXERCISE 1.2

EXERCISE 1.3

SOLUTIONS 1.1

SOLUTIONS 1.2

SOLUTIONS 1.3

CHAPTER 2 SEMICONDUCTORS IN NON EQUILIBRIUM

2.1 INTRODUCTION

2.2 CARRIER DRIFT

2.2.1 Motion of Carriers in a Crystal

2.2.2 Drift Current

2.3 CARRIER MOBILITY

2.3.1 Mobility due to Lattice Scattering

2.3.2 Mobility due to Ionized Impurity Scattering

2.3.3 Mobility Variation Due to Electric field

2.4 CONDUCTIVITY

2.5 RESISTIVITY

2.6 CARRIER DIFFUSION

2.6.1 Diffusion Current Density for Electron

2.6.2 Diffusion Current Density for Hole

2.6.3 Diffusion Length

2.7 TOTAL CURRENT DENSITY

2.8 THE EINSTEIN RELATION

2.9 BAND BENDING

2.10 QUASI-FERMI LEVELS

2.11 OPTICAL PROCESSES IN SEMICONDUCTORS

2.11.1 Absorption

2.11.2 Emission

2.12 AMBIPOLAR TRANSPORT

2.13 HALL EFFECT

2.13.1 Hall Field

2.13.2 Hall Voltage

2.13.3 Hall Coefficient

2.13.4 Applications of Hall effect

EXERCISE 2.1

EXERCISE 2.2

EXERCISE 2.3

SOLUTIONS 2.1

SOLUTIONS 2.2

SOLUTIONS 2.3

CHAPTER 3 PN JUNCTION DIODE

3.1 INTRODUCTION

3.2 BASIC STRUCTURE OF THE pn-JUNCTION

3.2.1 Space Charge Region in pn junction

3.3 ZERO APPLIED BIAS

3.3.1 Energy Band Diagram for Zero Biased pn junction

3.3.2 Built-in Potential Barrier for Zero Biased pn junction

3.3.3 Electric Field in Space Charge Region

3.3.4 Space Charge Width

3.4 REVERSE APPLIED BIAS

3.4.1 Energy Band Diagram for Reverse Biased pn Junction

3.4.2 Potential Barrier for Reverse Biased pn Junction

3.4.3 Space Charge Width

3.4.4 Electric Field

3.4.5 Junction Capacitance

3.5 FORWARD APPLIED BIAS

3.5.1 Energy Band Diagram for Forward Biased pn Junction

3.5.2 Excess Carrier Concentration

3.5.3 Ideal pn Junction Current

3.5.4 Ideal Current-Voltage Relationship

3.6 SMALL-SIGNAL MODEL OF THE pn JUNCTION

3.6.1 Diffusion Resistance

3.6.2 Small-Signal Admittance

3.7 COMPARISON BETWEEN PN JUNCTION CHARACTERISTICS FOR ZERO BIAS, REVERSE BIAS, AND FORWARD BIAS

3.8 JUNCTION BREAKDOWN

3.8.1 Zener Breakdown

3.8.2 Avalanche Breakdown

3.9 TURN-ON TRANSIENT

3.10 SOME SPECIAL PN JUNCTION DIODE

3.10.1 Tunnel Diode

3.10.2 PIN Diode

3.10.3 Varactor Diode

3.10.4 Schottky Diode

3.11 THYRISTORS

3.11.1 Silicon Controlled Rectifier (SCR)

3.12 TRIAC

3.13 DIAC

EXERCISE 3.1

EXERCISE 3.2

EXERCISE 3.3

SOLUTIONS 3.1

SOLUTIONS 3.2

SOLUTIONS 3.3

CHAPTER 4 BJT

4.1 INTRODUCTION

4.2 BASIC STRUCTURE OF BJT

4.2.1 Typical Doping Concentrations for BJT

4.2.2 Depletion Region

4.3 TRANSISTOR BIASING

4.3.1 Active Region

4.3.2 Saturation Region

4.3.3 Cut-off Region

4.3.4 Reverse Active Region or Inverse Region

4.4 OPERATION OF BJT IN ACTIVE MODE

4.4.1 Transistor Current Relation

4.5 MINORITY CARRIER DISTRIBUTION

4.5.1 Minority Carrier Distribution in Forward Active mode

4.5.2 Minority Carrier Distribution in Cut-Off Mode

4.5.3 Minority Carrier Distribution in Saturation Mode

4.5.4 Minority Carrier Distribution in Reverse Active Mode

4.6 CURRENT COMPONENTS IN BJT

4.6.1 DC Common-Base Current Gain

4.6.2 Small Signal Common Base Current Gain

4.6.3 Common Emitter Current Gain

4.7 EARLY VOLTAGE

4.8 BREAKDOWN VOLTAGE

4.8.1 Punch-Through Breakdown

4.8.2 Avalanche Breakdown

4.9 IMPORTANT PROPERTIES AND STANDARD CONSTANTS

EXERCISE 4.1

EXERCISE 4.2

EXERCISE 4.3

SOLUTIONS 4.1

SOLUTIONS 4.2

SOLUTIONS 4.3

CHAPTER 5 MOSFET

5.1 INTRODUCTION

5.2 TWO TERMINAL MOS STRUCTURE

5.3 ENERGY BAND DIAGRAM FOR MOS CAPACITOR

5.3.1 Energy Band Diagram for MOS Capacitors with the p-type Substrate

5.3.2 Energy Band Diagram for MOS Capacitors with the n-type Substrate

5.4 DEPLETION LAYER THICKNESS

5.4.1 Space Charge Width for p-type MOSFET

5.4.2 Space Charge Width for n-type MOSFET

5.5 WORK FUNCTION DIFFERENCES

5.5.1 Work Function Difference for p-type MOS Capacitors

5.5.2 Work Function Difference for n-type MOS Capacitors

5.6 FLAT BAND VOLTAGE

5.7 THRESHOLD VOLTAGE

5.7.1 Threshold Voltage for MOS Structure with p-type Substrate

5.7.2 Threshold Voltage for MOS Structure with n-type Substrate

5.8 DIFFERENTIAL CHARGE DISTRIBUTION FOR MOS CAPACITOR

5.8.1 Differential Charge Distribution in Accumulation Region

5.8.2 Differential Charge Distribution in Depletion Region

5.8.3 Differential Charge Distribution in Inversion Region

5.9 CAPACITANCE-VOLTAGE CHARACTERISTICS OF MOS CAPACITOR

5.9.1 Frequency Effects on C -V Characteristics

5.10 MOSFET STRUCTURES

5.11 CURRENT-VOLTAGE RELATIONSHIP FOR MOSFET

5.11.1 n-channel Enhancement Mode MOSFET for VGS < VT

5.11.2 n-channel Enhancement Mode MOSFET for VGS > VT

5.11.3 Ideal Current-Voltage Relationship for MOSFET

5.11.4 Transconductance

5.12 IMPORTANT TERMS

5.13 IMPORTANT CONSTANTS AND STANDARD NOTATIONS

EXERCISE 5.1

EXERCISE 5.2

EXERCISE 5.3

SOLUTIONS 5.1

SOLUTIONS 5.2

SOLUTIONS 5.3

CHAPTER 6 JFET

6.1 INTRODUCTION

6.2 BASIC CONCEPT OF JFET

6.2.1 n-channel JFET

6.2.2 p-channel JFET

6.3 BASIC JFET OPERATION

6.3.1 JFET Operation for Constant VDS and Varying VGS

6.3.2 JFET Operation for VGS = 0 and Varying VDS

6.4 DEVICE CHARACTERISTIC

6.4.1 n-channel JFET Characteristic

6.4.2 p-channel JFET Characteristic

6.5 IDEAL DC CURRENT-VOLTAGE RELATIONSHIP FOR DEPLETION MODE JFET

6.6 TRANSCONDUCTANCE OF JFET

6.7 CHANNEL LENGTH MODULATION

6.7.1 Depletion Legnth

6.7.2 Small Signal Output Impedance

6.8 EQUIVALENT CIRCUIT AND FREQUENCY LIMITATIONS

6.8.1 Small-Signal Equivalent Circuit

6.8.2 Frequency Limitation Factors and Cutoff Frequency

EXERCISE 6.1

EXERCISE 6.2

EXERCISE 6.3

SOLUTIONS 6.1

SOLUTIONS 6.2

SOLUTIONS 6.3

CHAPTER 7 INTEGRATED CIRCUIT

7.1 INTRODUCTION

7.2 BASIC MONOLITHIC INTEGRATED CIRCUIT

7.3 FABRICATION OF A MONOLITHIC CIRCUIT

7.4 EPITAXIAL GROWTH

7.5 OXIDATION

7.5.1 Dry oxidation

7.5.2 Wet oxidation

7.6 MASKING AND ETCHING

7.7 DIFFUSION OF IMPURITIES

7.7.1 Diffusion Law

7.7.2 Complementary Error Function

7.7.3 The Gaussian Distribution

7.8 ION IMPLANTATION

7.9 THIN FILM DEPOSITION

7.9.1 Evaporation

7.9.2 Sputtering

7.9.3 Chemical Vapor Deposition (CVD)

7.10 PN JUNCTION DIODE FABRICATION

7.11 TRANSISTOR CIRCUIT

7.11.1 Monolithic Integrated Circuit Transistor

7.11.2 Discrete Planar Epitaxial Transistor

EXERCISE 7.1

EXERCISE 7.2

EXERCISE 7.3

SOLUTIONS 7.1

SOLUTIONS 7.2

SOLUTIONS 7.3


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